/*+***********************************************************************************
 Filename: 9k_mcu01_mycore_v002\src\mem\zh_rom_async_v01.v
 Description: rom with async read implement by verilog.
   With initial code instructions.
              
 Modification:
   2025.08.16 Creation   H.Zheng

Copyright (C) 2025  Zheng Hui (hzheng@gzhu.edu.cn)

License: MulanPSL-2.0

***********************************************************************************-*/

module zh_rom_async_v01 #(parameter ROM_SIZE_IN_KB=1)(
  input wire [clogb2(ROM_SIZE_IN_KB*256-1)-1:0] addr,
  output wire [31:0] dout


);

//storage
  reg [7:0] BRAM[0:ROM_SIZE_IN_KB*1024-1];

  initial begin
    $readmemh("code.txt", BRAM);
  end

  wire [clogb2(ROM_SIZE_IN_KB*256-1)+1:0] addr_b0 = {addr,2'b00};
  wire [clogb2(ROM_SIZE_IN_KB*256-1)+1:0] addr_b1 = {addr,2'b01};
  wire [clogb2(ROM_SIZE_IN_KB*256-1)+1:0] addr_b2 = {addr,2'b10};
  wire [clogb2(ROM_SIZE_IN_KB*256-1)+1:0] addr_b3 = {addr,2'b11};

  assign dout = { BRAM[addr_b3], BRAM[addr_b2], BRAM[addr_b1], BRAM[addr_b0]};


//
function integer clogb2;
    input integer depth;
        for (clogb2=0; depth>0; clogb2=clogb2+1)
            depth = depth >> 1;
endfunction

endmodule